The escalating requirements for high densification and performance associated with ultra large scale integration semiconductor devices require design features of 0.25 microns and under, such as 0.18 microns, increased transistor and circuit speeds, high reliability and increased manufacturing throughput. The reduction of design features to 0.25 microns and under challenges the limitations of conventional interconnection technology, including conventional photolithographic, etching and deposition techniques.
Conventional methodology for forming patterned metal layers comprises a subtractive etching or etch back step as the primary metal patterning technique. Such a method involves the formation of a first dielectric layer on a semiconductor substrate, typically monocrystalline silicon, with conductive contacts formed therein for electrical connection with an active region on the semiconductor substrate, such as a source/drain region. A metal layer, such as aluminum or an aluminum alloy, is deposited on the first dielectric layer, and a photoresist mask is formed on the metal layer having a pattern corresponding to a desired conductive pattern. The metal layer is then etched through the photoresist mask to form the conductive pattern comprising metal features separated by gaps, such as a plurality of metal lines with interwiring spacings therebetween. A dielectric layer is then applied to the resulting conductive pattern to fill in the gaps and the surface is planarized, as by conventional etching or chemical-mechanical polishing (CMP) planarization techniques.
As shown in FIGS. 1 and 2, conventional practices comprise depositing metal layer 11 on dielectric layer 10 which is typically formed on a semiconductor substrate containing an active region with transistors (not shown) After photolithography, etching is then conducted to form a patterned metal layer comprising metal features 11a, 11b, 11c and 11d with gaps therebetween. A dielectric material 12, such as spin on glass (SOG), is typically deposited to fill in the gaps between the metal features, and baked at a temperature of about 300.degree. C. to about 450.degree. C., for a period of time up to about two hours, depending upon the particular SOG material employed, to effect planarization. Planarization, as by CMP, is then performed.
As feature sizes, e.g., metal lines and interwiring spacings, shrink to 0.25 microns and below, such as 0.18 microns, it becomes increasingly difficult to satisfactorily fill in the interwiring spacings voidlessly and obtain adequate step coverage. It also becomes increasingly difficult to form a reliable interconnection structure. A through-hole is typically formed in a dielectric layer to expose an underlying metal feature, wherein the metal feature serves as a landing pad occupying the entire bottom of the through-hole. Upon filling the through-hole with conductive material, such as a metal plug to form a conductive via, the entire bottom surface of the conductive via is in direct contact with the metal feature. Such a conventional technique is illustrated in FIG. 3, wherein metal feature 30 of a first patterned metal layer is formed on first dielectric layer 31 and exposed by through-hole 32 formed in second dielectric layer 33. In accordance with conventional practices, through-hole 32 is formed so that metal feature 30 encloses the entire bottom opening, thereby serving as a landing pad for metal plug 34 which fills through-hole 32 to form conductive via 35. Thus, the entire bottom surface of conductive via 35 is in direct contact with metal feature 30. Conductive via 35 electrically connects metal feature 30 and metal feature 36 which is part of a second patterned metal layer. As shown in FIGS. 2 and 3, the side edges of a metal feature or conductive line, e.g., 30A, 30B, and 36A, and 36B, taper somewhat as a result of etching.
The reduction of design features to the range of 0.25 microns and under requires extremely high densification. The conventional practice of forming a landing pad completely enclosing the bottom surface of a conductive via utilizes a significant amount of precious real estate on a semiconductor chip which is antithetic to escalating high densification requirements. In addition, it is extremely difficult to voidlessly fill through-holes having such reduced dimensions because of the extremely high aspect ratio, i.e., height of the through-hole with respect to diameter of the through-hole. Accordingly, conventional remedial techniques comprise purposely widening the-diameter of the through-hole to decrease the aspect ratio. As a result, misalignment occurs wherein the bottom surface of the conductive via is not completely enclosed by the underlying metal feature. This type of via is called a "borderless via", which also conserves chip real estate.
The use of borderless vias, however, creates new problems. For example, as a result of misalignment, the SOG gap filling layer is penetrated by etching when forming a through-hole, due to the low density and poor stability of SOG. As a result of such penetration, moisture and gas accumulate thereby increasing the resistance of the interconnection. Moreover, spiking can occur, i.e., penetration of the metal plug to the substrate, causing a short. For example, adverting to FIG. 4, first dielectric layer 41 is formed on substrate 40 and a first metal pattern comprising a first metal feature, e.g., metal line 45, is formed on first dielectric layer 21 gap filled with SOG 42. Dielectric layer 43 is then deposited and a through-hole formed therein exposing a portion of the upper surface and at least a portion of a side surface of first metal feature 45 and exposing a portion of SOG 42. Upon filling the through-hole with a metallic plug 44, typically comprising an initial barrier layer (not shown) and tungsten, spiking occurs, i.e., penetration through to substrate 40, thereby causing shorting.
Another problem generated by reducing the size of metal lines below about 0.25 microns is that it becomes increasingly difficult to voidlessly gap fill interwiring spacings with a dielectric material, such as SOG. Hydrogen silsesquioxane (HSQ) offers many advantages for use in interconnect patterns. HSQ is relatively carbon free, thereby avoiding poison via problems. Moreover, the absence of carbon renders it unnecessary to etch back HSQ below the upper surface of the metal lines to avoid shorting. In addition, HSQ exhibits excellent planarity and is capable of gap filling interwiring spacings less than 0.15 microns employing conventional spin-on equipment. HSQ undergoes a melting phase at approximately 200.degree. C., but does not convert to the high dielectric constant glass phase until reaching temperatures of about 400.degree. C. for intermetal applications and about 700.degree. C. to about 800.degree. C. for premetal applications.
However, the use of HSQ presents problems, particularly in borderless via applications. Typically, when forming a borderless via, a photoresist mask is deposited and the through-hole etched to expose a portion of an upper surface and a portion of a side surface of a metal line. The photoresist mask is then stripped employing an oxygen (O.sub.2)-containing plasma. It was found that the O.sub.2 -containing plasma employed to strip the photoresist mask degraded the HSQ layer so that, upon subsequent introduction of a barrier material, such as titanium nitride or titanium-titanium nitride, spiking occurred, i.e., the barrier material penetrated through the HSQ layer.
HSQ typically contains between about 70% and about 90% Si--H bonds. However, upon exposure to an O.sub.2 -containing plasma, a considerable number of Si--H bonds are broken and Si--OH bonds are formed. Upon treatment with an O.sub.2 -containing plasma, as much as about 20% to about 30% of the Si--H bonds in the as deposited HSQ film are broken. In addition, it was found that exposure to an O.sub.2 -containing plasma increased the moisture content of the as deposited HSQ film and its propensity to absorb moisture. An HSQ film having reduced Si--H bonds and high Si--OH bonds tends to absorb moisture from the ambient, which moisture outgases during subsequent barrier metal deposition. Thus, it was found that during subsequent barrier metal deposition, outgasing occurred thereby creating voids leading to incomplete electrical connection.
In copending application Ser. No.08/951,592, filed on Oct. 16, 1997, a method is disclosed for restoring degradation of an HSQ film by exposure to an H.sub.2 -containing plasma to increase the number of Si--H bonds, decrease the number of Si--OH bonds, and decrease the propensity to absorb moisture. The disclosed treatment with an H.sub.2 -containing plasma enables the use of HSQ to gap fill metal lines and form borderless vias with improved reliability increasing the reliability of the vias by reducing outgasing and, hence, void formation.
It was found, however, that HSQ does not exhibit sufficient etching resistance, particularly when etching to form a misaligned through-hole for a borderless via. As a result, during etching to form the misaligned through-hole, the etchant penetrates through the HSQ layer to the substrate. Upon filling the through-hole with conductive material, spiking occurs leading to shorting.
Accordingly, there exists a need to improve the etching resistance of a gap filled HSQ layer, thereby improving the reliability of borderless vias. There also exists a need for technology enabling the use of HSQ for gap filling metal features having dimensions below 0.25 microns in forming interconnection patterns comprising borderless vias without significantly increasing the dielectric constant of the HSQ layer.